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Introduction to CPLD and FPGA Design

Introduction to CPLD and FPGA Design

Software size:10M
Support platform:Windows/Linux/Unlix
Release time:2017-02-04 16:43:35
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Description

Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.

The first sections of this paper deals with the internal architecture and characteristics of these devices. Programmable logic devices are described in an overview, leading up to a detailed description of the Field Programmable Gate Array. The various architectures of these devices are examined in detail along with their tradeoffs, which allow you to decide which particular device is right for your design.

 

The next sections of this paper is about the design flow for an FPGA-based project. This section describes the phases of the design that need to be planned. This allows a designer or project manager to allocate resources and create a schedule.

 

The final sections of this paper discuss in detail, the design, simulation, and testing issues that arise when designing an FPGA. Understanding these issues will allow you to design a chip that functions correctly in your system and will be reliable throughout the lifetime of your product.

 

The Paper Contains The Below Details:

1. INTRODUCTION

2. THE MASKED GATE ARRAY ASIC

3. THE EVOLUTION OF PROGRAMMABLE DEVICES

    3.1 Programmable Read Only Memories (PROMs)

    3.2 Programmable Logic Arrays (PLAs)

    3.3 Programmable Array Logic (PALs)

    3.4 CPLDs and FPGAs

    3.5 Complex Programmable Logic Devices (CPLDs)

    3.6 Field Programmable Gate Arrays (FPGAs)

    3.7 Choosing Between CPLDs and FPGAs

4. THE DESIGN FLOW

    4.1 Writing a Specification

    4.2 Designing the chip

    4.3 Simulating - design review

    4.4 Synthesis

    4.5 Place and Route

    4.6 Resimulating - final review

    4.7 Testing

5. DESIGN ISSUES

    5.1 Top-Down Design

    5.2 Keep the Architecture in Mind

    5.3 Synchronous Design

    5.4 Floating Nodes

    5.5 Bus Contention

    5.6 One-Hot State Encoding

6. DESIGN FOR TEST (DFT)

    6.1 Testing Redundant Logic

    6.2 Initializing State Machines

    6.3 Observable Nodes

    6.4 Scan Techniques

    6.5 Built-In Self Test

    6.6 Signature Analysis

7. SIMULATION ISSUES

8. CONCLUSION

 

This paper intends to present an overview of CPLD and FPGA technologies, and give guidelines for developing a chip based on my experience designing for a large number of companies and a large number of applications. If all of these guidelines are followed, the chances of creating a working chip in a short time at minimum expense is excellent.


 

About The Author:

By Bob Zeidman

President

The Chalkboard Network

bob@chalknet.com

www.chalknet.com

 

 

You are welcomed to download this paper and hope it is of help to your CPLD and FPGA Design!


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